In communication systems, the evolvement of backplanes from bus-based architectures to fabric/mesh-based architectures has fueled rapid deployment of multi-gigabit serializer and de-serializer (SerDes) devices. The variations of backplane channels have greatly complicated the task of system optimization and performance tuning. This is especially true on networking and storage equipment with high channel count.
It has been shown that adjacent channels can have very different frequency responses due to channel variances such as, for example, layer connection, manufacturing, environmental elements and source and load termination interaction. It is therefore evident that for a given SerDes device, a common equalization setting will not work on all different backplanes, with or without process, voltage and temperature (PVT) variations.
Therefore, a systematic way of exploring design space is required to ensure one or more given performance goals are met and/or exceeded (optimized).